In the semiconductor industry, conventional patterning processes include patterning a photoresist layer by lithographic methods, such as photolithography, electron beam, or X-ray lithography, for mask definition. The pattern on the photoresist layer is subsequently transferred into a hard material in contact with the photoresist layer using a dry etch, wet etch, or lift-off technique. Photolithography is limited to forming features of approximately 90 nm with a 248 nm light, approximately 45 nm with a 193 nm light, and from approximately 25 nm to approximately 30 nm with a 13.7 nm (extreme ultraviolet (“EUV”)) light. The limitations on the resolution of conventional photolithography are due to the wavelength of radiation used in the process. In addition, photolithographic equipment becomes increasingly expensive as feature sizes become smaller. In contrast, electron beam lithography is capable of creating smaller features, such as features in the tens of nanometers range. With electron beam lithography, the features are generated at an earlier point in time than with conventional lithography. However, electron beam lithography is expensive and very slow.
As feature sizes on semiconductor devices become smaller, imprint lithography has been proposed as a replacement for photolithography. In imprint lithography, a template having a nanoscale pattern is pressed into a film on the semiconductor device. The pattern on the template deforms the film and forms a corresponding image in the film. After removing the template, the pattern in the film has been transferred to the semiconductor device. The size of the pattern on the template and of the corresponding features on the semiconductor device are substantially similar. Therefore, unlike photolithographic techniques where a mask or reticle pattern is reduced substantially (for example, 4×) in size when transferred to the surface of a semiconductor device, imprint lithography is considered a “1×” pattern transfer process because it provides no demagnification of the pattern on the template that is transferred to the semiconductor device surface. Templates for use in imprint lithography are known in the art, as described in U.S. Pat. No. 6,580,172 to Mancini et al. and U.S. Pat. No. 6,517,977 to Resnick et al., the disclosures of each of which patents are incorporated herein by reference. To form the high resolution pattern on the template, electron beam mask-making techniques are typically used. However, use of these techniques is undesirable because they are expensive and have low throughput.
As feature sizes on semiconductor devices approach sub-100 nm, there is a need for a fast, reliable, and cost effective method of making small features. Since imprint lithography is capable of forming small features, it would be desirable to more easily and cheaply produce templates for use in imprint lithography.